Regviz

Espressif Systems /ESP32-P4 /SPI2 /SPI_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SPI_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-P4/SPI2/SPI_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_DUMMY_OUT)SPI_DUMMY_OUT 0 (SPI_FADDR_DUAL)SPI_FADDR_DUAL 0 (SPI_FADDR_QUAD)SPI_FADDR_QUAD 0 (SPI_FADDR_OCT)SPI_FADDR_OCT 0 (SPI_FCMD_DUAL)SPI_FCMD_DUAL 0 (SPI_FCMD_QUAD)SPI_FCMD_QUAD 0 (SPI_FCMD_OCT)SPI_FCMD_OCT 0 (SPI_FREAD_DUAL)SPI_FREAD_DUAL 0 (SPI_FREAD_QUAD)SPI_FREAD_QUAD 0 (SPI_FREAD_OCT)SPI_FREAD_OCT 0 (SPI_Q_POL)SPI_Q_POL 0 (SPI_D_POL)SPI_D_POL 0 (SPI_HOLD_POL)SPI_HOLD_POL 0 (SPI_WP_POL)SPI_WP_POL 0SPI_RD_BIT_ORDER 0SPI_WR_BIT_ORDER

Description

SPI control register

Fields

SPI_DUMMY_OUT

0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.
SPI_FADDR_DUAL

Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
SPI_FADDR_QUAD

Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
SPI_FADDR_OCT

Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
SPI_FCMD_DUAL

Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
SPI_FCMD_QUAD

Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
SPI_FCMD_OCT

Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
SPI_FREAD_DUAL

In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.
SPI_FREAD_QUAD

In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.
SPI_FREAD_OCT

In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.
SPI_Q_POL

The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.
SPI_D_POL

The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.
SPI_HOLD_POL

SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
SPI_WP_POL

Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
SPI_RD_BIT_ORDER

In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.
SPI_WR_BIT_ORDER

In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data